1. Field of the Disclosure
The present disclosure generally relates to memory devices, and more particularly, to stacked-die memory devices.
2. Description of the Related Art
Memory bandwidth and latency are significant performance bottlenecks in many processing systems. These performance factors may be improved to a degree through the use of stacked-die memory (also called three-dimensional (3D) memory), which provides increased bandwidth and reduced intra-device latency through the use of through-silicon vias (TSVs) to interconnect multiple stacked dies of memory. System memory and other large-scale memory typically are implemented as separate from the other components of the system. A system implementing stacked-die memory therefore can continue to be bandwidth-limited due to the bandwidth of the interconnect connecting the stacked-die memory to the other components and latency-limited due to the propagation delay of the signaling traversing the relatively-long interconnect and the handshaking process needed to conduct such signaling. The inter-device bandwidth and inter-device latency have a particular impact on processing efficiency and power consumption of the system when a performed task requires multiple accesses to the stacked-die memory, such as a search operation or other query operation on a key-value store, as each access requires a back-and-forth communication between the stacked-die memory and a processor, and thus the inter-device bandwidth and latency penalties are incurred twice for each access.